Offers a design and verification environment for C/C++ with synthesis to VHDL and Verilog code.
VHDL compilers and design environments, including Windows, DOS and Linux support.
Provides tools for aiding Verilog development. Including The Temporal Rover for automatic verification of protocols and Verilog Java PLI.
Includes papers, presentations, conference publications and SAVANT VHDL, a free VHDL analyser and simulator. From University of Cincinnati.
Offers ASIC and FPGA design and verification services, drivers and tools. Includes product and service overview and PDF detailed product specifications available.
Training and consultancy across Europe in VHDL, Verilog, SystemC, Perl and Tcl/Tk. Offers free resources for hardware designers.
The Verilog-AMS Technical Subcommittee has been created with the charter to develop, update and promote analog and mixed signal extensions to the Verilog (IEEE-1364) language.
Science /
Technology /
Electronics /
Design /
Hardware_Description_Languages /
Verilog
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